The present invention relates to a method for making a flexible electrical connective device having multiple levels of conductive paths or any similar multi-layer electrical device. One type of such a device includes an array of conductive pads on at least one major surface. These conductive pads may be each connected to one of a more widely spaced array of connective tabs along the sides of the device. There are many applications for this type of device. For example, such a device may be used to provide a rectilinear array of pads for testing of ball grid array (BGA) modules or circuit boards with BGA interconnect patterns that are too small to be tested by conventional pin probe testers. Another application is to provide for interconnection to a similarly patterned array of independently connectable electrical contact pads in an electrically stimulated array. The requirement that the electrical contact pads be independently connectable creates a conductive path routing and cross-talk suppression challenge.
One use for a planar array of independently connectable electrical contact pads is for electrical stimulation of, and electrical reception from, an ultrasound array. For a more complete description of the requirements for a connector to an ultrasound array, please see U.S. Pat. No. 5,855,049, issued Jan. 5, 1999, which is hereby incorporated by reference as if fully set forth herein. As noted in this reference, it is typical to use a flex circuit electrical contact pad array for the purpose of electrically connecting an ultrasound array to take advantage of the acoustical and mechanical characteristics of a flex circuit. A flex circuit can permit a full set of connections without suffering the effects of the gaps that can be created by slight non-uniformities between two rigid surfaces. In addition, the flex circuit can be flexibly routed to connect the array to external circuit boards or cabling.
A flexible array of electrical contacts also proves useful in the stimulation of a set of nerve cells in an animal body or in serving as a conductive link for the recording of nerve impulses from a set of nerve cells. Among the bodily sites having an array of nerve cells that may require stimulation are the retina and the nerves that stimulate the muscles. In addition, the cochlea, an organ of the inner ear that translates sound waves into electric nerve impulses may host a cochlear implant. This type of implant, which stimulates cochlear nerve endings in people for whom the hearing train has been severed so that sound waves do not stimulate the auditory nerves, has been available for many years. There is a continuing effort, however, to increase the density of electrodes in cochlear implants and other electrical implants, in order to effect a more complete sensory or stimulation restoration. Along these lines, a method of constructing a flexible planar array of electrodes that is thinner than was heretofore available may prove very helpful. Other medical applications include providing an array of contacts for a biochemical or other biophysical sensing system.
Another use for an array of independently connectable electrical contact pads is for attachment to the terminals of an integrated circuit (IC) die. IC dies are typically produced having a set of terminals along the periphery of the die and with the terminals mutually spaced apart by 50 to 100 microns. The die is typically placed in a package to form an outside interconnect pitch of 1.27 mm or smaller, for connection to a PCB. The IC die terminals are typically connected to an intermediate chip scale package circuit by means of wire bonding or by flip chip mounting to a flex circuit that expands outwardly from the die perimeter to a larger rectilinear array. The principle reason why the IC die terminals are arranged solely along the perimeter of the IC die is because of the limitations of wire bonding and flex circuit manufacturing technology. If a flex circuit having a partial or full rectilinear array of interconnect pads with a pitch on the order of tens of microns could be efficiently produced, this would permit IC dies to be produced having terminals in a matching array, thereby permitting more terminals into and out of the IC, a highly desirable goal.
IC wafer test provides another area of application for a flex circuit with an array of conductive contact pads. Before the IC wafer is diced there is no periphery for each individual IC, for electrical connections to be made. Consequently, all electrical connections must be made along the planar surfaces of the IC. Accordingly, a flex circuit bearing a planar array of contacts, because it has the flexibility to forgive protrusional variations, is the ideal mechanism for forming a number of such planar electrical contacts simultaneously.
Yet another application for a planar array of independently connectable electrical contact pads, is in the testing of PCBs. It is highly desirable to test a PCB after production but prior to connecting circuitry to the PCB. If a flaw in the PCB is discovered after circuitry has been connected to the PCB, the entire circuit must typically be discarded. For a PCB having a tightly pitched array of terminals for connecting to a ball grid array, however, it may be extremely difficult to form a test connector that independently contacts each one of these terminals. It would, therefore, be highly desirable to have a tightly packed planar array of independently connectable electrical contact pads for the purpose of forming a test connector for a PCB bearing tightly packed arrays of electrical contact pad contacts or to convert the tightly pitched array of terminals to a less tightly packed array which can be tested by conventional means. In addition, a tightly packed planar array of electrical contact pads can also be used to test the ball grid array IC circuit itself.
One method used to construct planar arrays of independently connectable electrical contact pads is known as the “thin film\wet chemistry” process of building up a flex circuit layer by layer. Each dielectric layer is spin coated on to the top of the previously created laminate structure, then drilled or etched, plated and patterned. For via interconnects, a pad is first formed on a deposited layer for connection to the prospective next layer to be deposited. After the next layer is deposited a blind via is drilled to the underlying pad, followed by plating and patterning of a pad directly over the via, forming an electrical connection to the pad below. The disadvantages of this method are that it is expensive and a mistake on any layer can ruin the entire flex circuit. The process of spin coating a patterned layer is also somewhat problematic as the spin coating must be applied to at least a minimum thickness for the certain covering of all electrical features, thereby setting a minimum thickness for the finished multilevel circuit.
Another traditional method to construct planar arrays of independently connectable electrical contact pads has been to join together conductively patterned dielectric layers each having mutually co-located connective pads. Individual patterned dielectric layers are first bonded together, typically through an intermediate dielectric, followed by via drilling and plating through the mutually co-located electrical contact pad pads to connect one layer to the next. Typically the connective paths are patterned to allow through-hole drilling to connect layers. As additional layers are added they are drilled and plated to form connections. There are two principle problems associated with this method. First, many process steps are involved to drill and plate the various layers. Second, the accuracy required to align the various layers and successfully drill and plate to connect them severely limits the array density. If through-hole drilling instead of blind vias are used to connect layers, the traces must be routed so as to avoid drilling through traces running above or below the layer to be connected, further limiting the array density.
Yet an additional method of constructing an array of contact pads interconnected through a multilayer structure involves laminating patterned circuits together using anisotropic or z-axis adhesives which connect conductive portions of the individual layers together without forming a conductive short to neighboring traces. A disadvantage of this approach is the additional complexity involved in laying out the conductive circuit patterns as well as the higher cost and uncertain reliability of the anisotropic connective approach.
U.S. Pat. No. 6,354,000, issued on Mar. 12, 2002, addresses many of the concerns noted above. This patent describes a process in which a stack of layers bearing conductive paths are electrically connected to a top layer bearing an array of electrical contact pads by drilling and plating connective vias. Although this technique represents a great advance over the prior art, some problems have arisen in the implementation of this method of construction. For example, the patterned sheets may tend to warp during lamination. Also, it is a challenge to drill through several layers without drilling through a conductor on a layer interposed between the drilling surface and the target conductive path. In addition, some target conductive paths may be by necessity very thin, on the order of microns, presenting a challenge to one attempting to accurately drill a via to the target conductive path. One more problem is posed by the possibility of a trace piercing and adjacent dielectric layer and thereby contacting a trace on the adjacent layer. This potential problem necessitates the use of thicker dielectric layers than would otherwise be necessary, thereby forcing a greater thickness for the device as a whole.
A problem that is faced by those practicing any one of the techniques described above is that of completely electrically isolating traces from one another. In the case of traces that are on the same level, imperfections in photolithographic technique can cause traces to effectively extend farther transversely than the ideal trace extent indicated by the mask. These unintended “shoulders” force a sparser design than would be otherwise possible, to avoid unintended trace contact. Another type of unwanted trace contact may occur between the traces on the bottom of a first lamina and the traces on the top of a second lamina that is positioned directly beneath the first lamina. To avoid this type of contact, it is necessary to use an adhesive thickness (in joining the two lamina) that includes an error budget for uneven adhesive thickness and uneven trace thickness. Alternatively, a product that is a sheet of material that is tough on the inside but malleable on the outside may be used. Both techniques, again, reduce circuit density.
The present invention addresses these limitations as described below.